First silicon experiments within wafers

Typical industrial practice blocks experiments by lot and treats wafers as homogeneous units. This work demonstrates the practical advantages of varying some factors within wafer. The case study involves an advanced microprocessor, the response of greatest interest is speed, and its critical gate lengths are manipulated by exposure changes within wafer. The experiment is constructed using a spatial design criterion and a constrained optimal design algorithm. Data analysis has 3 steps: (a) for each wafer, model the response as a function of both within-wafer factors and (x,y) coordinates. (b) For each wafer and factor level, average over all site coordinates and other factor levels. (c) across wafers, fit a response surface. An example illustrates, and several practical issues are highlighted