A new cryptographic system and its VLSI implementation

Nowadays, there are many cryptographic applications that demand high security, high speed, and low hardware cost. In order to meet the requirements, we propose a new cryptographic system. Under the control of an unpredictable binary sequence generated from 1D Logistic map, every 7 bytes of input data are 1) expanded to 8 bytes, ii) randomly swapped in three level, 3) randomly XORed or XNORed to two random keys Seed1 or Seed2, and 4) bit-recirculated in random direction and random number of bits. It is analyzed to be high security. In order to implement the system, a unified architecture with 5 stages pipeline for the system has been designed, verified, and physically realized based on a 0.35 μm CMOS technology. Finally, the implementation result is compared with some existing designs.