Title :
Optimized embedded memory diagnosis
Author :
De Carvalho, M. ; Bernardi, P. ; Reorda, M. Sonza ; Campanelli, N. ; Kerekes, T. ; Appello, D. ; Barone, M. ; Tancorre, V. ; Terzi, M.
Author_Institution :
Dip. di Autom. e Inf., Politec. di Torino, Torino, Italy
Abstract :
This paper describes an optimized embedded memory diagnosis flow that exploits many levels of knowledge to produce accurate failure hypothesis. The proposed post-processing analysis flow is composed of many steps investigating failure shapes as well as cell fail syndromes, and includes advanced techniques to tackle incomplete data possibly due to tester noise and/or by faults showing intermittent effects. The effectiveness of the technique is demonstrated on an automotive-oriented System-on-Chip (SoC) manufactured in a 90nm technology by STMicroelectronics, which includes embedded SRAM memory cores tested using a programmable BIST. Scrambled BITMAPS gives a visual feedback leading to quick physical defect identification. Such research is relevant to aid on the manufacturing, material and process enhancements raising silicon yield.
Keywords :
built-in self test; embedded systems; system-on-chip; STMicroelectronics; automotive-oriented system-on-chip; failure hypothesis; intermittent effects; optimized embedded memory diagnosis; programmable BIST; scrambled BITMAPS; Arrays; Built-in self-test; Circuit faults; Failure analysis; Shape; Software; System-on-a-chip; Embedded memory diagnosis; Failure Bitmaps; Failure analysis; Fault models; Scrambling;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783109
