DocumentCode
3368165
Title
Max-Fill: A method to generate high quality delay tests
Author
Fan, X. ; Reddy, S.M. ; Pomeranz, I.
Author_Institution
Dept. of ECE, Univ. of Iowa, Iowa City, IA, USA
fYear
2011
fDate
13-15 April 2011
Firstpage
375
Lastpage
380
Abstract
It was recently observed that the methods to generate scan based tests with low switching activity cause about 40% less activity than functional tests. Thus such tests may cause test escapes as they may not adequately stress the circuits under test. In this work we propose a method called Max-Fill to generate high quality partially-functional broadside delay tests. The generated tests are shown to cause switching activity close to the switching activity during functional operation. The method computes a set of reachable states in which states are likely to cause high switching activity. During test generation phase, these states are used as background states to fill the unspecified bits of test cubes. Additionally, the number of test patterns produced is less than that produced by low power test methods. Experimental results for ISCAS-89 circuits are given.
Keywords
automatic test pattern generation; boundary scan testing; delays; ISCAS-89 circuits; background states; circuits under test; functional operation; high quality delay tests; max-fill; partially-functional broadside delay tests; scan based tests; switching activity; test generation phase; test patterns; Circuit faults; Radio frequency; Switches; delay tests; partially-functional tests; reachable states; switching activity;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location
Cottbus
Print_ISBN
978-1-4244-9755-3
Type
conf
DOI
10.1109/DDECS.2011.5783114
Filename
5783114
Link To Document