Yield enhancement through photoresist characterization at the implant photo operations

This paper will demonstrate the ability to positively impact yield of an IC device through means of photoresist characterization at the implant photo processes. Film characterization and DOE methodology will be used to optimize the photo pattern. Device yield will be measured by means of defects associated with the Vgs Parameter of the device, a parameter that monitors voltage at the gate and source as a function of drain current. Optimizing the photoresist process at the photo implant layers creates a more robust process which provides stability for the Vgs parameter of the device. The end results are an increasing process yield for the product