Title :
Validation and optimization of TMR protections for circuits in radiation environments
Author :
Ruano, O. ; Maestro, J.A. ; Reviriego, P.
Author_Institution :
Univ. Antonio Nebrija, Madrid, Spain
Abstract :
A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.
Keywords :
circuit optimisation; electronic engineering computing; integrated circuit reliability; radiation effects; SEU; TMR protections; optimization processes; radiation environments; software fault injection; solution area cost; Circuit faults; Integrated circuit reliability; Optimization; Registers; Single event upset; Tunneling magnetoresistance; Error Rate (ER); Single Event Upsets (SEUs); Triple Modular Redundancy (TMR); fault injection; optimization;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on
Conference_Location :
Cottbus
Print_ISBN :
978-1-4244-9755-3
DOI :
10.1109/DDECS.2011.5783120
