Design of high-precision FFT based on VHDL and analysis of code coverage

Author

Jun Cheng

Author_Institution

Coll. of Phys. & Inf. Sci., Hunan Normal Univ., Changsha, China

Volume

7

fYear

2011

fDate

12-14 Aug. 2011

Firstpage

3579

Lastpage

3582

Abstract

This paper uses structured design to implement the floating-FFT by VHDL with ISE5.3 and simulates it by ModelSim. The data pathways in this project are in the form of 32-bit single precision format which can avoid data overflow and achieve high SNR. In this project, the Radix-2 algorithm is used and the controller is modeled as a finite state machine. The simulation and code coverage analysis results show that (1) the design can achieve high accuracy; (2) the running speed is fast enough to meet the real-time signal processing requirements, and (3) the test work is very complete.

Keywords

digital arithmetic; fast Fourier transforms; finite state machines; hardware description languages; real-time systems; signal processing; 32-bit single precision format; ISE5.3; ModelSim; Radix-2 algorithm; VHDL; code coverage analysis; data overflow; data pathway; finite state machine; floating FFT; high accuracy design; high precision FFT; real-time signal processing requirement; structured design; Analytical models; Clocks; Data models; Process control; Random access memory; Signal processing algorithms; Simulation; VHDL; code coverage; floating FFT; high precision;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic and Mechanical Engineering and Information Technology (EMEIT), 2011 International Conference on

Conference_Location

Harbin, Heilongjiang

Print_ISBN

978-1-61284-087-1

Type

conf

DOI

10.1109/EMEIT.2011.6023838

Filename

6023838