Implementation of dual latency operation in VDSL2 with downstream power back off on DSP chip

VDSL2 employs a dual latency where voice and video traffic are directed over two separate bearer channels. In this paper a new scheme that partitions the tones over the two latency paths based on SNR with down stream power back off (DPBO) is presented. The bit loading is done from the obtained SNR profile using the standard rate adaptive water filling, accounting the fractional bits. Results include bit loading pattern, data rates for the two latency paths with DPBO and implementation of the same on the TMS DSP processor 6713.