Title :
A Design of Decoded Picture Buffer of H.264 Based on DDR2
Author :
Dang Xinxin ; Chen Li
Author_Institution :
Sch. of Inf. Sci. & Technol., Northwest Univ., Xi´an, China
Abstract :
In the H.264/AVC video decoding chip, in the face of the massive decoded picture data, it is impossible to ignore the increase in production costs and unlimited storage space. Therefore, in this paper, designing of a cycle buffer for the storage and presentation of the decoded pictures. The key technology is the calculation of maximum decoded picture buffer, storage method of a decoded picture, and the design of the cycle buffer. Also, do a verification of the design.
Keywords :
video coding; DDR2; H.264-AVC video decoding chip; cycle buffer; decoded picture buffer; storage method; Buffer storage; Decoding; Field programmable gate arrays; Real-time systems; Streaming media; TV; Video sequences; DDR2; H.264; H.264 video decoding core; decoded picture buffer; prototype verification;
Conference_Titel :
Computational Intelligence and Security (CIS), 2013 9th International Conference on
Conference_Location :
Leshan
Print_ISBN :
978-1-4799-2548-3
DOI :
10.1109/CIS.2013.109
