A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders

We propose a 16-bit Booth Leapfrog array multiplier with low voltage (1.1 V), low power dissipation (10.8 μW/MHz) and relatively high-speed (64 ns) operation. We achieve these attributes in two ways. First, we employ our proposed low hardware complexity Dynamic Adders (DAs) where their Sum and Carry outputs are obtained at different rates and the DAs are used to reduce the spurious switching in the multiplier. Second, we place most of these DAs in a Leapfrog array structure (in the first stage adder array) and employ a high-speed Manchester Carry Look-Ahead (CLA) adder as the Carry Propagation Adder (CPA). The proposed multiplier features the lowest power dissipation, one of the shortest delays, resulting in the lowest Power-Delay-Product (PDP) when compared to reported designs. The proposed multiplier is suitable for power- and IC area-critical applications such as a hearing instrument.