DocumentCode :
336918
Title :
A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation
Author :
Hsiao, Shen-Fu ; Shiue, Wei-Ren
Author_Institution :
Inst. of Comput. & Inf. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume :
4
fYear :
1999
fDate :
15-19 Mar 1999
Firstpage :
1929
Abstract :
A recursive algorithm for computation of both forward and backward DFT has been proposed where the common entries in the decomposed matrices are factored out in order to reduce the number of multipliers needed during implementation. The derived algorithm is essentially the band-matrix-vector multiplication with matrix bandwidth of 3. By exploiting the heterogeneous dependency graphs for the matrix-vector multiplication and using an efficient mapping technique, only log2 N adders and log2N-1 multipliers are needed to compute the DFT of size N, a great saving from a previously proposed systolic architecture which calls for 3log2N adders and 3log2 N multipliers. Furthermore, due to the simplicity and regularity of the architectures, it is possible to design a low power processor by turning off the hardware components of no operation at proper time steps. VLSI implementation of the DFT/IDFT processor with distributed finite state machine (FSM) for timing control is also presented
Keywords :
CMOS digital integrated circuits; VLSI; adders; digital arithmetic; digital signal processing chips; discrete Fourier transforms; finite state machines; inverse problems; matrix multiplication; multiplying circuits; timing; CMOS technology; DFT/IDFT computation; DSP; VLSI implementation; adders; algorithm; backward DFT; band-matrix-vector multiplication; decomposed matrices; distributed FSM; efficient mapping technique; forward DFT; heterogeneous dependency graphs; high-throughput architecture; low power architecture; matrix bandwidth; matrix-vector multiplication; multipliers; recursive algorithm; systolic architecture; timing control; Computer architecture; Discrete Fourier transforms; Frequency; Hardware; Matrix decomposition; Power engineering and energy; Power engineering computing; Systolic arrays; Turning; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1999. Proceedings., 1999 IEEE International Conference on
Conference_Location :
Phoenix, AZ
ISSN :
1520-6149
Print_ISBN :
0-7803-5041-3
Type :
conf
DOI :
10.1109/ICASSP.1999.758302
Filename :
758302
Link To Document :
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