ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation

Author

Galy, Ph ; Jimenez, J. ; Meuris, P. ; Schoenmaker, W. ; Dupuis, O.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2011

fDate

2-4 May 2011

Firstpage

1

Lastpage

4

Abstract

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM.

Keywords

CMOS integrated circuits; capacitance; electrostatic discharge; elemental semiconductors; silicon; CMOS technology; ESD RF parasitic capacitance; ESD RF protections; analogue IO pad; electrostatic discharge protection; frequency 10 GHz to 20 GHz; parasitic capacitance; silicon measurements; voltage 1 kV to 2 kV; Electrostatic discharge; Equations; Mathematical model; Parasitic capacitance; Radio frequency; Silicon; Thyristors; Diode; ESD; RF; S parameters; SCR; dual SCR Maxwell equations;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2011 IEEE International Conference on

Conference_Location

Kaohsiung

ISSN

Pending

Print_ISBN

978-1-4244-9019-6

Type

conf

DOI

10.1109/ICICDT.2011.5783184

Filename

5783184