A new parallel DSP with short-vector memory architecture

Author

Fridman, Jose ; Anderson, William C.

Author_Institution

Analog Devices Inc., Norwood, MA, USA

Volume

4

fYear

1999

fDate

15-19 Mar 1999

Firstpage

2139

Abstract

This paper presents a new highly-parallel DSP architecture based on a short-vector memory system developed at Analog Devices, Inc. This DSP incorporates for the first time in an embedded processor a number of techniques found in general purpose computing, such as branch prediction, deep and fully interlocked pipeline, and SIMD instruction execution. By means of its short-vector high-bandwidth memory system it is able to deliver sustained performance that is close to its peak computational rates of 1.5 GFLOPS (32-bit floating-point), or 6 GOPS (16-bit fixed-point)

Keywords

digital signal processing chips; fixed point arithmetic; floating point arithmetic; memory architecture; parallel architectures; pipeline processing; vector processor systems; 1.5 GFLOPS; 16 bit; 32 bit; Analog Devices; DSP chips; SIMD instruction execution; branch prediction; deep interlocked pipeline; embedded processor; fixed-point operation; floating-point operation; fully interlocked pipeline; general purpose computing; parallel DSP architecture; peak computational rates; performance; short-vector high-bandwidth memory system; short-vector memory system; Bandwidth; Computer architecture; Digital signal processing; Digital signal processing chips; Embedded computing; Finite impulse response filter; Memory architecture; Pipelines; Registers; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1999. Proceedings., 1999 IEEE International Conference on

Conference_Location

Phoenix, AZ

ISSN

1520-6149

Print_ISBN

0-7803-5041-3

Type

conf

DOI

10.1109/ICASSP.1999.758357

Filename

758357