DocumentCode
3369621
Title
Special considerations for 3DIC circuit design and modeling
Author
Liu, Sally ; Peng, Yung-Chow ; Hsueh, Fu-Lung
Author_Institution
Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
fYear
2011
fDate
2-4 May 2011
Firstpage
1
Lastpage
4
Abstract
In this paper, the new elements in 3DIC are examined for enabling optimal 3D products: including 3D interconnect which maybe the limiting factor to achievable speed; 3D chip design strategy (partition and implementation) to achive optimal performance; wireless testing to address the challenges in testing a partial system / chip before stacking and with limited observation points after stacking.
Keywords
three-dimensional integrated circuits; 3D chip design strategy; 3D interconnect; 3DIC circuit design; 3DIC circuit modeling; optimal 3D products; Couplings; Stacking; Substrates; Testing; Three dimensional displays; Through-silicon vias; Wireless communication; 3D interconnect; design strategy; wireless testing;
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design & Technology (ICICDT), 2011 IEEE International Conference on
Conference_Location
Kaohsiung
ISSN
Pending
Print_ISBN
978-1-4244-9019-6
Type
conf
DOI
10.1109/ICICDT.2011.5783200
Filename
5783200
Link To Document