A novel FPGA architectural implementation of pipelined thinning algorithm

Author

Hsiao, Pei-Yung ; Hua, Chun-Ho ; Lin, Chien-Chen

Author_Institution

Dept. of Electron. Eng., Chang Gung Univ., Tao Yuan, Taiwan

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

Thinning is a very important operation in the image preprocessing stage of pattern recognition. This investigation presents an improved thinning algorithm and its FPGA architectural implementation. The improved algorithm based on parallel pipelined design is adapted and formulated such that it is suitable to computing architecture implementation. The FPGA-based architecture extends the applicability of this algorithm in the area of real time image processing. Using the proposed Modification Unit Array, this work performs thinning operation within 0.07 sec at 40 MHz for a 512×512 picture.

Keywords

field programmable gate arrays; image recognition; image thinning; pipeline processing; real-time systems; 0.07 sec; 40 MHz; FPGA architectural implementation; Modification Unit Array; computing architecture; image preprocessing; parallel pipelined design; pattern recognition; pipelined thinning algorithm; real time image processing; Algorithm design and analysis; Biomedical image processing; Computer architecture; Concurrent computing; Electronics industry; Field programmable gate arrays; Image processing; Industrial electronics; Pattern recognition; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329341

Filename

1329341