Balanced Truncation of a stable non-minimal deep-submicron CMOS interconnect

As the widening of process variability in submicron CMOS technology calls for accurate timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. In this context, model order reduction techniques have been used extensively to reduce the complexity of extracted interconnect circuits and to expedite fast and accurate circuit simulation. In the interconnect modeling, solving large-scale Lyapunov equations arises as a necessity in model order reduction techniques based on Balanced Truncation. In this paper, within this framework, dominant eigensubspaces of the product of the system Gramians are approximated directly. We construct orthogonal basis sets for the dominant subspaces of controllability and observability Gramians and perform eigenvalue decomposition to reduce the cost of singular value decomposition. As the experimental results indicate, the proposed approach can significantly reduce the complexity of interconnect, while retaining high accuracy in comparison to the original model.