The impact of clock gating schemes on the power dissipation of synthesizable register files

In this paper, the power dissipation of synthesizable register files with respect to different clock gating schemes is examined. Clock gating is a well-known technique for power reduction of sequential circuits. Although different clock gating schemes exist, there is no fundamental difference in the power dissipation of sequential logic because the data input signals of disabled flip-flops do not change when the clock signal is disabled. However, it is shown here that in contrast to sequential logic the clock gating scheme has significant impact on the power dissipation of register files due to signal changes of the data input port. The major result of this work is that the power dissipation of register files can be reduced significantly, if a clock gating scheme different from that one usually recommended for sequential logic is applied.