DocumentCode :
3369817
Title :
Design evaluation of injection enhancement gate transistor based on device simulation
Author :
Yahata, M. R o ; Eicher, Simon
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fYear :
1998
fDate :
3-6 Jun 1998
Firstpage :
265
Lastpage :
268
Abstract :
The on-state voltage and the turn-off loss were simulated for many kinds of injection enhancement gate transistors (IEGTs) with different trench-MOS channel mobilities (μeff), trench depths and thin-out ratios. It has been found that a high μeff, a deep trench and a small thin-out ratio are effective in improving the trade-off between on-state voltage and turn-off loss
Keywords :
carrier mobility; insulated gate bipolar transistors; isolation technology; losses; power bipolar transistors; semiconductor device models; IEGTs; design evaluation; device simulation; injection enhancement gate transistor; on-state voltage; thin-out ratio; trench depth; trench-MOS channel mobility; turn-off loss; Cathodes; Charge carrier lifetime; Charge carrier processes; Circuit simulation; Electrodes; Laboratories; Protons; Semiconductor devices; Transistors; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on
Conference_Location :
Kyoto
ISSN :
1063-6854
Print_ISBN :
0-7803-4752-8
Type :
conf
DOI :
10.1109/ISPSD.1998.702684
Filename :
702684
Link To Document :
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