DocumentCode :
3369833
Title :
Low power dual matchline ternary content addressable memory
Author :
Mohan, Nitin ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume :
2
fYear :
2004
fDate :
23-26 May 2004
Abstract :
Content addressable memories (CAMs) are very attractive for high-speed table lookups in modern network systems. This paper presents a low-power dual match line (ML) ternary CAM (TCAM) to address the power consumption issue of CAMs. The highly capacitive ML is divided into two segments to reduce the active capacitance and hence the power. We analyze possible cases of mismatches and demonstrate a significant reduction in power (up to 43%) for a small penalty in search speed (4%).
Keywords :
CMOS memory circuits; integrated circuit modelling; low-power electronics; power consumption; storage allocation; capacitance; content addressable memory; low power dual matchline ternary; modern network systems; power consumption; Associative memory; CADCAM; Cams; Capacitance; Computer aided manufacturing; Energy consumption; Laser sintering; Logic; Multilevel systems; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
Type :
conf
DOI :
10.1109/ISCAS.2004.1329351
Filename :
1329351
Link To Document :
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