Determination of worst case input combinations of nanoscale circuits using Bayesian networks

As MOSFETs are scaled down to nanometer dimensions, their performances and behaviours become less predictable. Designing reliable circuit or systems using these nano-transistors (nano-circuits or systems) post new challenges and require paradigm shift in design techniques, process and flow. In conventional circuits, the inputs of digital circuits were deterministic but as MOSFET technology enter into nanoscale dimensions, the behaviour of inputs become probabilistic in nature. The major source of distorted inputs are the transient errors and signal noises. The probabilistic inputs´ random behaviour needs to be modelled into softwares so that a circuit designer can predict the exact reason of reliability-degradation. These probabilistic inputs can be modelled mathematically in the form of distributed inputs and called as Probabilistic Digital Inputs (PDIs). This research work shows the modelling of probabilistic inputs to determine their worst and best case input combinations for few benchmark circuits.