DocumentCode
3369993
Title
65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications
Author
Le-Coz, J. ; Flatresse, P. ; Clerc, S. ; Belleville, M. ; Valentian, A.
Author_Institution
STMicroelectronics, Crolles, France
fYear
2011
fDate
2-4 May 2011
Firstpage
1
Lastpage
4
Abstract
This work presents a partially depleted Silicon-on-Insulator (PD-SOI) low-static power consumption Retention Flip-Flop (REFF). This flip-flop is designed in order to avoid wake-up transient glitches. In addition specific leakage reduction techniques are used to compensate the extra leakage currents induced by the SOI floating body effects. This leads to a static power consumption reduced by 2 for only 6% of extra silicon area, compared to a regular floating body implementation.
Keywords
CMOS integrated circuits; flip-flops; power semiconductor switches; silicon-on-insulator; MTCMOS power switch applications; PD-SOI glitch-free retention flip-flop; low-static power consumption retention flip-flop; partially depleted silicon-on-insulator; size 65 nm; specific leakage reduction; wake-up transient glitches; Degradation; Delay; Flip-flops; Leakage current; Logic gates; Power demand; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design & Technology (ICICDT), 2011 IEEE International Conference on
Conference_Location
Kaohsiung
ISSN
Pending
Print_ISBN
978-1-4244-9019-6
Type
conf
DOI
10.1109/ICICDT.2011.5783222
Filename
5783222
Link To Document