A novel CMOS double-edge triggered flip-flop for low-power applications

Author

Sung, Yu-Yin ; Chang, Robert C.

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

A novel low-power double-edge triggered flip-flop is presented in this paper. Low-power and high-speed flip-flops are required in many applications, especially in SoC systems. Double-edge triggered flip-flop can latch the data signal changes both from high to low and low to high. Thus, lower clock frequency is used while the data throughput is preserved. The proposed flip-flop uses a low-swing clock technology and low-Vt transistors for the clock transistors to reduce the leakage current problem. Beside, only a single latch is used and lower power consumption is achieved. HSPICE simulation results show that the power dissipation of the proposed flip-flop is reduced by at least 28% and the power-delay product is also reduced by at least 50%.

Keywords

CMOS logic circuits; SPICE; clocks; flip-flops; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; leakage currents; logic design; logic simulation; low-power electronics; system-on-chip; CMOS double-edge triggered flip-flop; HSPICE simulation; SoC systems; clock frequency; clock transistors; data signal change; high-speed flip-flops; latches; leakage current problem; low-Vt transistors; low-power applications; low-swing clock technology; power consumption; power dissipation; power-delay product; Circuit simulation; Clocks; Delay; Energy consumption; Flip-flops; Frequency; Latches; Leakage current; Power dissipation; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329359

Filename

1329359