An efficient implementation of D-Flip-Flop using the GDI technique

Author

Morgenshtein, Arkadiy ; Fish, Alexander ; Wagner, Israel A.

Author_Institution

Dept. of Electr. Eng., Technion, Haifa, Israel

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

A new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique is presented. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI DFF, as compared to other methods. A variety of circuits have been implemented in 0.35 μm and 0.1 μm technologies to compare the proposed GDI structure with existing alternatives, showing an up-to 45% reduction in power-delay product in GDI. Properties of implemented circuit are discussed and simulation results are reported.

Keywords

CMOS logic circuits; flip-flops; integrated circuit design; integrated circuit modelling; logic design; logic simulation; 0.1 micron; 0.35 micron; DFF design; GDI structure; Gate-Diffusion-Input technique; efficient D-Flip-Flop; logic design; power dissipation; power-delay product; CMOS technology; Circuit simulation; Delay; Laboratories; Latches; Logic design; MOSFETs; Power dissipation; Standards development; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329361

Filename

1329361