Low power pattern generation for BIST architecture

A new low power test pattern generator using a linear feedback shift register (LFSR), called LP-TPG, is presented to reduce the average and peak power of a circuit during test. The correlation between the test patterns generated by LP-TPG is more than conventional LFSR. LP-TPG inserts intermediate patterns between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of primary inputs which eventually reduces the switching activities inside the circuit under test, and hence, power consumption. The random nature of the test patterns are kept intact. The area overhead of the additional components to the LFSR is negligible compared to the large circuit sizes. The experimental results are shown for ISCAS85 benchmarks, confirming up to 63% and 27% reduction in average and peak power, respectively.