High performance sense amplifier circuit for low power SRAM applications

Author

Chow, Hwang-Cherng ; Chang, Shu-Hsien

Author_Institution

Dept. of Electron. Eng., Chang Gung Univ., Tao-Yuan, Taiwan

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this paper. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35 μm CMOS process can work at 100 MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3 V, the simulations show that this design has 14% and 63% power delay product improvement over the prior art and conventional sense amplifier, respectively.

Keywords

CMOS integrated circuits; SRAM chips; amplifiers; integrated circuit design; low-power electronics; 0.35 micron; 100 MHz; 3.3 V; CMOS process; integrated circuit design; low power SRAM applications; low voltage operation; power delay product; sense amplifier circuit; sensing delay; Art; Circuits; Decoding; Delay; High power amplifiers; Low voltage; Power amplifiers; Power dissipation; Power engineering and energy; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329378

Filename

1329378