Title :
Effects of PECVD oxide process in the sandwiched SOG structure on MOSFET hot-carrier reliability
Author :
Allman, D. ; Han, L.K. ; Kwong, D.L.
Author_Institution :
Symbios Logic Inc., Colorado Springs, CO, USA
fDate :
31 May-2 Jun 1995
Abstract :
In this paper, we have systematically investigated the effect of PECVD oxide process in the sandwiched SOG structure for interlevel dielectric applications on MOSFET hot-carrier reliability. Both silane-based oxide (OX) and tetraethylorthosilicate-based oxide (TEOS) were used to form various combinations with SOG as interlevel dielectrics. The influence of N2O (N2O-TEOS) and O 2 (O2-TEOS) as the source gas of oxygen during the PECVD TEOS deposition was also studied. Results indicate that O2 TEOS/SOG/O2TEOS increases the number of electron traps in the gate oxide and deteriorate SiO2-Si interface endurance, thus reducing device lifetime. In addition, the use of OX to replace any one of the O2-TEOS layers improves hot-carrier immunity considerably. Finally, N2O-TEOS/SOG/OX is shown to be a very promising process due to its conformal nature over OX/SOG/OX and improved reliability over O2-TEOS/SOG/OX
Keywords :
MOSFET; dielectric thin films; electron traps; hot carriers; plasma CVD; plasma CVD coatings; semiconductor device metallisation; semiconductor device reliability; MOSFET hot-carrier reliability; N2O; O2; PECVD oxide process; SiO2-Si; SiO2/Si interface endurance; TEOS; device lifetime; electron traps; gate oxide; hot-carrier immunity; interlevel dielectric applications; sandwiched SOG structure; silane-based oxide; spin-on glass; tetraethylorthosilicate-based oxide; CMOS technology; Degradation; Dielectrics; Encapsulation; Hot carrier effects; Hot carriers; MOSFET circuits; Planarization; Stress; Threshold voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524657
