VLSI design of dual-mode Viterbi/turbo decoder for 3GPP

Author

Huang, Kai ; Li, Fan-Min ; Shen, Pei-Ling ; Wu, An-Yeu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

In this paper, a prototype design of a dual-mode Viterbi/turbo decoder for 3rd generation wireless communication systems is proposed. By merging some similar modules in both the Viterbi decoder and the log-MAP turbo code decoder, we built one dual-mode decoder with both of these two functions. When the decoder operates in the turbo mode, early-termination control of the iteration process can reduce the power consumption without influencing the decoding accuracy. Besides, in order to conform to the CDMA2000 standard, our decoder can also perform as a reconfigurable Viterbi decoder. That is, our design meets the requirement of the multi generator polynomial convolutional code specification. The design provides an integrated FEC kernel for modern communication systems.

Keywords

3G mobile communication; VLSI; Viterbi decoding; channel coding; convolutional codes; dual codes; forward error correction; iterative decoding; mobile radio; telecommunication standards; turbo codes; 3rd generation wireless communication systems; VLSI design; cdma2000 standard; channel coding; dual mode decoder; integrated FEC kernel; iterative decoding; log-MAP turbo code decoder; modern communication systems; multigenerator convolutional code; polynomial convolutional code; power consumption; prototype design; reconfigurable Viterbi decoder; Communication system control; Convolutional codes; Energy consumption; Iterative decoding; Merging; Prototypes; Turbo codes; Very large scale integration; Viterbi algorithm; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329386

Filename

1329386