A low power high speed accumulator for DDFS applications

An accumulator optimised for use in a Direct Digital Frequency Synthesis (DDFS) system with 24 bits of frequency resolution and 13 bits of phase resolution is presented. Update rates in excess of 800 MHz are achieved by careful choice of architecture. Power dissipation is lowered by removing redundant circuitry. The static, D-type flip flops used in the pipeline architecture are the dominant source of power dissipation. Hence the refresh-every-cycle operation of accumulators in DDFS is exploited by using dynamic delay elements to reduce power consumption.