A low power high speed accumulator for DDFS applications

Author

Chappell, Michael ; McEwan, Alistair

Author_Institution

Dept. of Eng. Sci., Oxford Univ., UK

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

An accumulator optimised for use in a Direct Digital Frequency Synthesis (DDFS) system with 24 bits of frequency resolution and 13 bits of phase resolution is presented. Update rates in excess of 800 MHz are achieved by careful choice of architecture. Power dissipation is lowered by removing redundant circuitry. The static, D-type flip flops used in the pipeline architecture are the dominant source of power dissipation. Hence the refresh-every-cycle operation of accumulators in DDFS is exploited by using dynamic delay elements to reduce power consumption.

Keywords

adders; delay circuits; direct digital synthesis; flip-flops; low-power electronics; memory architecture; parallel architectures; pipeline processing; power consumption; D-type flip flops; direct digital frequency synthesis; dynamic delay elements; frequency resolution; high speed accumulator; low power accumulator; phase resolution; pipeline architecture; power dissipation; refresh-every-cycle operation; Adders; Biomedical engineering; Circuits; Delay; Energy consumption; Frequency synthesizers; Physics; Pipeline processing; Power dissipation; Read only memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329392

Filename

1329392