DocumentCode
3370556
Title
The use of multithreading for exception handling
Author
Zilles, Craig B. ; Emer, Joel S. ; Sohi, Gurindar S.
Author_Institution
Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
fYear
1999
fDate
1999
Firstpage
219
Lastpage
229
Abstract
Common hardware exceptions, when implemented by trapping, unnecessarily serialize program execution in dynamically scheduled superscalar processors. To avoid the consequences of trapping the main program thread, multithreaded CPUs can exploit control and data independence by executing the exception handler in a separate hardware context. The main thread doesn´t squash instructions after the excepting instruction, conserving fetch bandwidth and allowing execution of instructions independent of the exception. This leads to earlier branch resolution in the post exception code and additional memory latency tolerance. As a proof of concept, using threads to handle software TLB misses is shown to provide performance approaching that of an aggressive hardware TLB miss handler
Keywords
exception handling; multi-threading; parallel architectures; TLB misses; branch resolution; exception handling; memory latency tolerance; multithreaded CPUs; multithreading; post exception code; Application software; Bandwidth; Costs; Delay; Hardware; Multithreading; Resource management; Retirement; Software performance; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 1999. MICRO-32. Proceedings. 32nd Annual International Symposium on
Conference_Location
Haifa
ISSN
1072-4451
Print_ISBN
0-7695-0437-X
Type
conf
DOI
10.1109/MICRO.1999.809460
Filename
809460
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