DocumentCode
3370624
Title
VLSI-efficient implementation of full adder-based median filter
Author
Burian, Adrian ; Takala, Jarmo
Author_Institution
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Volume
2
fYear
2004
fDate
23-26 May 2004
Abstract
A new VLSI-suitable hardware implementation of the median filter that uses full adders (FAs) as the basic building block is introduced. The proposed hardware structures consist of several stages that exhibit regular and modular structure. It also reduces the hardware requirements and has a faster processing speed, when compared with some other existing hardware implementations. A general methodology for designing full adder-based median filters is also developed.
Keywords
VLSI; adders; integrated circuit design; median filters; VLSI; basic building block; faster processing speed; full adder based median filter design; hardware implementation; Adders; Application software; Birth disorders; Computer architecture; Computer networks; Design methodology; Digital filters; Hardware; Integrated circuit interconnections; Sorting;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329397
Filename
1329397
Link To Document