Implementation of digital IF receiver based on SDR using DSP builder

Author

Wenmiao, Song

Author_Institution

Commun. & Electron. Dept., North China Electr. Power Univ., Baoding, China

fYear

2011

fDate

1-3 Nov. 2011

Firstpage

266

Lastpage

269

Abstract

A digital IF receiver is researched based on the idea of Software defined radio in this paper. The receiver includes numerical controlled oscillator(NCO), Digital Down Conversion(DDC) and the modem in a Wireless Spread Spectrum Communication system. Firstly the DDC module which include CIC (cascaded-integrator-com) and HBF(half band filter) is implemented through DSP builder, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board. Then the coherent demodulation of QPSK based on COSTAS loop is researched and designed in FPGA using modern DSP technology.

Keywords

application specific integrated circuits; digital signal processing chips; integrated circuit design; logic design; oscillators; software radio; spread spectrum communication; ASIC; COSTAS loop; DDC module; DSP builder; FPGA board; QPSK; SDR; application specific integrated circuit design flow; cascaded-integrator-com; coherent demodulation; digital IF receiver; digital down conversion; field programmable gate array; half band filter; modem; modern DSP technology; numerical controlled oscillator; software defined radio; wireless spread spectrum communication system; Demodulation; Digital signal processing; Filtering theory; Finite impulse response filter; IIR filters; Phase shift keying; Receivers; Costas LOOP; DDC; digital IF;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave, Antenna, Propagation, and EMC Technologies for Wireless Communications (MAPE), 2011 IEEE 4th International Symposium on

Conference_Location

Beijing

Print_ISBN

978-1-4244-8265-8

Type

conf

DOI

10.1109/MAPE.2011.6156164

Filename

6156164