DocumentCode
3370880
Title
Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits
Author
Kakani, Vasanth ; Dai, Foster F. ; Jaeger, Richard C.
Author_Institution
Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
Volume
2
fYear
2004
fDate
23-26 May 2004
Abstract
This paper presents a delay analysis for Current Mode Logic (CML) circuits operating at the GHz range. The optimal biasing for CML circuits is obtained considering the circuit speed and power consumption. We propose and analyze a novel "keep alive" CML circuit that biases the upper level transistors at the slightly higher current than the lower level transistors. A speed improvement of about 11% at low bias range is demonstrated using the proposed biasing scheme.
Keywords
current-mode circuits; current-mode logic; delay estimation; high-speed integrated circuits; low-power electronics; power consumption; power transistors; CML circuit; circuit speed; current mode logic circuit; delay analysis; keep alive biasing; optimal biasing; power consumption; upper level transistors biasing; CMOS logic circuits; Circuit noise; Circuit topology; Energy consumption; Frequency; Logic circuits; Logic design; Propagation delay; Semiconductor device modeling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1329410
Filename
1329410
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