DocumentCode
3371194
Title
Chip-to-chip communications using capacitive interconnects
Author
Viitala, Olli ; Ryynänen, Jussi
Author_Institution
Dept. of Micro & Nanosci., Aalto Univ., Aalto, Finland
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
2888
Lastpage
2891
Abstract
This paper presents a transceiver for capacitive interconnects between two chips. The capacitive link model was simulated with an EM-simulator and a lumped circuit model was developed from the simulations. The channel model was then used in the design of the transceiver. The designed transceiver was implemented in 65-nm CMOS and the chip stack was assembled with standard equipment. The paper also presents the BER measurement results for the transceiver.
Keywords
CMOS integrated circuits; error statistics; integrated circuit interconnections; lumped parameter networks; transceivers; BER measurement; CMOS process; EM simulator; bit error rate; capacitive interconnects; capacitive link model; channel model; chip stack; chip-to-chip communications; lumped circuit model; size 65 nm; transceiver design; Assembly; Bonding; Capacitors; Circuit simulation; Integrated circuit interconnections; Lead; Packaging; Parasitic capacitance; Semiconductor device modeling; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5536966
Filename
5536966
Link To Document