A phase-adjustable negative phase shifter using a single-shot locking method

Author

Wang, Chua-Chin ; Hsueh, Ya-Hsin ; Hong, Sen-Fu ; Kao, Rong-Sui

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

A digital negative phase shifter circuit is present to provide negative delays (phase shift) in order to avoid multi-locking hazards. It can adjust the negative phase by using multiplexers and voltage variable delay cells to select the required phase shift. The design is implemented by 0.35 μm CMOS 1P4M technology. A single-shot locking method is adopted to reduce the locking time. Most important of all, the negative phase shift is predictable and adjustable. The simulation results show that the accuracy of the proposed design is better than 6%.

Keywords

CMOS digital integrated circuits; delay lock loops; delays; integrated circuit design; integrated circuit testing; phase shifters; 0.35 micron; CMOS technology; digital negative phase shifter circuit; multiplexers; negative phase shift delay; phase adjustable negative phase shifter; single shot locking method; voltage variable delay cells; CMOS technology; Clocks; Delay; Frequency synthesizers; Hazards; Jitter; Phase shifters; Pulse generation; Signal design; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329426

Filename

1329426