Title :
Low power and area efficient semi-digital PLL for low bandwidth applications
Author :
Dietl, Markus ; Sareen, Puneet
Author_Institution :
Clock & Timing Products, Texas Instrum., Freising, Germany
Abstract :
Conventional low bandwidth Phase lock loop uses an external Capacitor together with a big on chip ripple capacitor. A new architecture of a Phase lock loop is proposed which eliminates the need for an external capacitor. Also the value of the on chip capacitor is reduced drastically, reducing the chip size. The PLL architecture proposed uses very low power.
Keywords :
phase locked loops; area efficient semi-digital PLL; chip ripple capacitor; external capacitor; low bandwidth application; low bandwidth phase lock loop; low power semi-digital PLL; Bandwidth; Capacitors; Charge pumps; Computer architecture; Microprocessors; Phase locked loops; Voltage-controlled oscillators; Low power; Phase lock loop; Real time clock;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-8500-0
DOI :
10.1109/VDAT.2011.5783546
