DocumentCode
3371683
Title
Variation-aware deep nanometer gate performance modeling: An analytical approach
Author
Chen, Min ; Yi, Yang ; Zhao, Wei ; Ma, Dian
Author_Institution
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
fYear
2011
fDate
25-28 April 2011
Firstpage
1
Lastpage
4
Abstract
A complete set of analytical gate performance models is developed based on driving current analysis. Closed-form equations for gate delay and output slew are obtained, which capture the dependence on key process and design parameters, such as the input slew, threshold voltage, etc. Using these formulas, gate performance of various topologies is accurately predicted under both nominal and variational conditions. This work can be easily implemented to enhance fast statistical timing analysis, circuit optimization and aging characterization.
Keywords
ageing; integrated circuit modelling; nanoelectronics; statistical analysis; aging characterization; circuit optimization; closed-form equations; design parameters; driving current analysis; gate delay; output slew; statistical timing analysis; variation-aware deep nanometer gate performance modeling; Analytical models; Delay; Integrated circuit modeling; Load modeling; Logic gates; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on
Conference_Location
Hsinchu
ISSN
Pending
Print_ISBN
978-1-4244-8500-0
Type
conf
DOI
10.1109/VDAT.2011.5783560
Filename
5783560
Link To Document