Modeling multi-output filtering effects in PCMOS

A methodology has been proposed recently to predict error rates of cascade structures of blocks in Probabilistic CMOS (PCMOS). It requires characterization of unique probabilistic blocks to predict the error rates of a multi-block cascade structure. While the technique was shown to work for a probabilistic carry-select adder, the technique needs a new model to work in a Wallace Tree Multiplier (WTM) where error propagates not only along the carry bit but also along the sum bit of the basic full adder building block utilized. In this paper we present a new model for characterization of probabilistic circuits/blocks and present a procedure to find and characterize unique circuits/blocks. Unlike prior approaches, our new model distinguishes distinct filtering effects per output. We apply the proposed model to a WTM and show that using our model, the methodology using a cascade structure can predict WTM error-rates with reasonable accuracy in PCMOS.