Design and VLSI implementation of MPEG audio decoder

Author

Tsai, Tsung-Han ; Chen, Thou-Ho ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1995

fDate

31 May-2 Jun 1995

Firstpage

206

Lastpage

210

Abstract

The paper presents a chip design for an MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced to half of the original number, and the storage demand reduced too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words of memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using a silicon compiler structure in the Genesil system, with 0.8-μm CMOS technology

Keywords

CMOS digital integrated circuits; VLSI; audio coding; decoding; digital signal processing chips; quadrature mirror filters; 0.8 micron; CMOS technology; Genesil system; MPEG audio decoder; VLSI; adder-subtractor; chip design; multiplier-accumulator; polyphase filter bank; pseudo-QMF; silicon compiler; Chip scale packaging; Decoding; Filter bank; Mirrors; Phase change materials; Quantization; Silicon compiler; Standardization; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-2773-X

Type

conf

DOI

10.1109/VTSA.1995.524664

Filename

524664