• DocumentCode
    3371846
  • Title

    Recursively combine floorplan and Q-place in mixed mode placement based on circuit´s variety of block configuration

  • Author

    Yang, Changqi ; Hong, Xianlong ; Yang, Hannah Honghua ; Zhou, Qiang ; Cai, Yici ; Lu, Yongqiang

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • Volume
    5
  • fYear
    2004
  • fDate
    23-26 May 2004
  • Abstract
    Mixed mode placement (MMP) is characterized by a number of same-height standard cells mixed with scattering big blocks in a fixed die. The variety of size and number of blocks introduces challenges to existing algorithms in achieving reasonable solution quality and running time. A new design flow named recursive mixed mode placement (RMMP) is presented in this paper to provide a solution of MMP with this circuit´s variety of block configuration taken into account. It starts from recursively partitioning circuits to form a tree of virtual blocks in the different condition of the size and number of blocks as well as the logical or physical hierarchy. Then it combines floorplan on block level and quadratic place (Q-place) on cell level to complete the global placement. Our approach takes advantage of combining floorplan and Q-place algorithms to fit the variety of circuit´s components. The combined approach improves the algorithm efficiency and obtains satisfactory results of MMP in terms of wire length and running time on various industry and academia test cases.
  • Keywords
    integrated circuit layout; quadratic programming; trees (mathematics); Q-place algorithms; block configuration variety; block level floorplan; block size; cell level; circuit components; fixed die; global placement; logical hierarchy; physical hierarchy; quadratic place; recursive circuit partitioning; recursive mixed mode placement; running time; scattering big blocks; standard cells; tree forming; virtual blocks; wire length; Algorithm design and analysis; Circuit analysis; Computer science; Delay; Design methodology; Hidden Markov models; Law; Legal factors; Shape; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
  • Print_ISBN
    0-7803-8251-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.2004.1329463
  • Filename
    1329463