Scaling rules and parameter tuning procedure for analog design reuse in technology migration

In this paper a methodology for analog design reuse during technology scaling is proposed. First of all, analytical resizing rules are derived for MOS transistors working in saturation and triode regions. These rules, however, do not account for parasitic effects that, especially in submicron technologies, lead to inaccurate scaling. For this reason, for example, DC gain and unity gain frequency may substantially differ from the original. In order to compensate these inaccuracies, a tuning procedure based on SPICE simulations is proposed. Finally, the migration and tuning procedures are validated and simulation results are compared scaling down a Miller OTA from 0.25 μm to 0.15 μm technology.