A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications

Author

Ju, Chi-Cheng ; Chang, Yung-Chang ; Cheng, Chia-Yun ; Wang, Chih-Ming ; Lin, Hue-Min ; Chen, Chun-Chia ; Chiu, Fred ; Wang, Sheng-Jen

Author_Institution

Mediatek Inc., Hsinchu, Taiwan

fYear

2011

fDate

25-28 April 2011

Firstpage

1

Lastpage

4

Abstract

In this paper, an AVS-embedded multi-format video decoder is presented. It integrates AVS JP@L6.2, H.264 HP@L4.2, VC-1 AP@L3, and MPEG-2 MP@HL in a single chip and features resources sharing, memory management, and early-stage acqusition to facilitate cost and bandwidth efficiency. For the applications of broadcasting, an adaptive error concealment method is proposed. A chip is fabricated and integrates 415K logic gates and 682Kbits embeded SRAM in 65nm single-poly seven-metal CMOS process with area of 2.47mm². AVS video decoding of full 1920×1088 high-definition sequences at 60 frames per second is achieved at 166MHz clock frequency with power dissipation of 41.3mW at 1.0V supply voltage.

Keywords

CMOS integrated circuits; SRAM chips; broadcasting; codecs; embedded systems; home computing; logic gates; storage management; video coding; AVS JP@L6.2; AVS video decoding; AVS-embedded multiformat video decoder; H.264 HP@L4.2; MPEG-2 MP@HL; VC-1 AP@L3; adaptive error concealment method; broadcasting; clock frequency; digital home applications; early-stage acqusition; embeded SRAM; full-HD AVS-H.264-VC-1-MPEG-2 video decoder; high-definition sequences; logic gates; memory management; power dissipation; resources sharing; single chip; single-poly seven-metal CMOS process; Bandwidth; Decoding; Memory management; Multimedia communication; Random access memory; Streaming media; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Conference_Location

Hsinchu

ISSN

Pending

Print_ISBN

978-1-4244-8500-0

Type

conf

DOI

10.1109/VDAT.2011.5783591

Filename

5783591