Title :
A VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
Author :
Lee, Wen-Ta ; Chen, Thou-Ho ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
31 May-2 Jun 1995
Abstract :
The paper presents a novel transpose path metric (TPM) algorithm to reduce the interconnection routing complexity for a radix-2k Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rearrangement in a transpose strategy. With features of modulation and regularity, this algorithm is very suitable for VLSI implementation; consequently, a larger memory length VA decoder can be constructed with several smaller memory length modules. Finally, a VLSI architecture for a 16-states radix-4 VA decoder using TPM has been developed
Keywords :
VLSI; Viterbi decoding; digital signal processing chips; VLSI architecture; interconnection routing complexity; memory length; modulation; radix-2k Viterbi decoding; regularity; state permutation; transpose path metric algorithm; Bit error rate; Computer architecture; Convolutional codes; Decoding; Educational institutions; Error correction codes; Routing; Shift registers; Very large scale integration; Viterbi algorithm;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524667
