High performance DDR architecture in Intel® Core™ processors using 32nm CMOS high-K metal-gate process

This paper describes the DDR architecture in Intel® Core™ processors operating up to 1333MT/s and designed in 32nm process technology. The architecture uses adaptive techniques to achieve very low clock jitter (40% margin to spec), data scrambling to reduce simultaneous switching noise and novel training algorithms to improve I/O margins in the presence of crosstalk. A fast wakeup technique allows shutting down the receive path for finer grain power management, reducing standby power by 15%.