Placement and routing optimization for circuits derived from BDDs

The high complexity of circuits which currently consist of several millions of transistors, can only be managed using a concise design flow. Recently, the one-pass synthesis paradigm came up, i.e. to consider the whole design process as one flow instead of isolated steps. In this context, designing circuits based on the mapping of binary decision diagrams (BDDs) shows several advantages. While various BDD based approaches for logic minimization or design for testability have been proposed, in this paper we show that placement and routing of BDD circuits can be optimized at a high level of abstraction. Based on algorithms for reducing the number of nodes and edge crossings, we demonstrate on multiple benchmarks that significant improvements are possible in reasonable time.