DocumentCode
3372659
Title
Constructing Augmented Multimode Compactors
Author
Gizdarski, Emil
Author_Institution
Synopsys Inc., Mountain View, CA
fYear
2008
fDate
April 27 2008-May 1 2008
Firstpage
29
Lastpage
34
Abstract
In this paper, a new space compactor, called an augmented multimode compactor, is presented. Accordingly, scan chains are separated into groups using t orthogonal partitions. The augmented multimode compactor has three modes such that all scan chains, a group of scan chains and an intersection of two groups of scan chains is selected for compression. Respectively, 1, kt-1 and any number of unknown states per shift-out cycle can be tolerated in these modes where k is the number of the compactor outputs assigned for observation of each scan chain. Simulation results demonstrate the efficiency of the proposed principles for constructing fully X-tolerant compactors. In the range of 0 to 10 percent of unknown states in test responses, the proposed scheme achieved the same or up to 3 times better observability than the fully X-tolerant combinational compactor.
Keywords
combinational circuits; logic partitioning; logic testing; X-tolerant compactors; augmented multimode compactors; combinational circuits; orthogonal partitions; scan chains; space compactor; Circuit faults; Circuit testing; Combinational circuits; Compaction; Convolutional codes; Error correction; Linear code; Observability; Propagation losses; Very large scale integration; array codes; linear codes; on-chip compression; test data compression;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2008. VTS 2008. 26th IEEE
Conference_Location
San Diego, CA
ISSN
1093-0167
Print_ISBN
978-0-7695-3123-6
Type
conf
DOI
10.1109/VTS.2008.40
Filename
4511692
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