The RF receiver front-end chip design with the transformer balun for DSRC applications

Author

Huang, Jhin-Fang ; Jiangn, Yong-Jhen ; Liu, Ron-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan

fYear

2011

fDate

25-28 April 2011

Firstpage

1

Lastpage

4

Abstract

A 0.18 μm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB, the conversion gain of 17.5 dB, the (DSB) NF of 4.2 dB, and the third-order intercept point (IIP3) of -10 dBm at 5.8 GHz frequency. The chip area of the proposed receiver front-end including pads is 1.4 × 1.4 mm with the total power dissipation of 49.78 mW.

Keywords

CMOS integrated circuits; MMIC; baluns; integrated circuit design; microwave receivers; protocols; Colpitts VCO; DSRC protocols; IIP3; RF receiver front-end chip design; RFIC; current-reused LNA; dedicated short range communication protocol; folded Giber cell mixer; frequency 5.8 GHz; gain 17.5 dB; loss 30.5 dB; power 49.78 mW; size 0.18 mum; third-order intercept point; transformer balun; CMOS integrated circuits; Coils; Impedance matching; Mixers; Noise measurement; Receivers; Voltage-controlled oscillators; CMOS; DSRC; balun; front-end; receiver;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2011 International Symposium on

Conference_Location

Hsinchu

ISSN

Pending

Print_ISBN

978-1-4244-8500-0

Type

conf

DOI

10.1109/VDAT.2011.5783609

Filename

5783609