A 1.2 Gb/s recursive polyphase cascaded integrator-comb prefilter for high speed digital decimation filters in 0.18-μm CMOS

Recursive polyphase cascaded integrator-comb (CIC) prefilters are proposed to greatly increase the speed of digital decimation so as to address demands of high speed sigma-delta ADCs that over-sample at several GHz. The recursive computations in the new method avoid the substantial area/complexity increases in traditional polyphase decomposition implementations. Clock rate improvements by factors of 2 or 4 can be achieved, in comparison to those of traditional CIC filters. Implemented in a 0.18-μm CMOS process, a decimate-by-16 prefilter achieves a 1.2 Gb/s clock rate in the slow corner after post-route extraction, while occupying 0.08 mm² area.