A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code

This work presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.