Design of PLL behavioral model based on the Verilog-A

With the development of integrated circuits and SOC (System on Chip, the system-level Chip) technology to appear, the traditional circuit-level PLL can´t simulate precisely in the current EDA tools. So, this paper puts forward a method based on Verilog-A behavior-level modeling method to solve the problem. According to the mathematical model of VCO and three-order passive loop low-pass filter, establish the behavior models based on Verilog-A, pack and embed them to ADS, achieving the phase lock loop system design which composes center frequency of 120 MHz VCO, cut-off frequency for 200 kHz of LPF and others modules. Verify the PLL system model in ADS platform, the simulation results prove that building behavior models for analog modules based on Verilog-A not only can greatly shorten the simulation time, quickening design process, but also can effectively improve the simulation accuracy. This method has an important reference value for integrated circuit researcho.