Silicon Undercut Characterization in a CMOS-MEMS Process

This paper describes a convenient and inexpensive electrical test structure to characterize silicon undercut in a CMOS-MEMS process, which helps to define the context-dependent MEMS design rules. Undercut extracted from electrical measurements match physical undercut measured from focused- ion beam etched cross sections and optical observations. Silicon undercut increases with silicon isotropic etch time and opening size, and it varies slightly with structural height. An exponential equation is employed to model the relation between undercut and opening size. Based on the characterization results, MEMS design rules are extracted.